1. Field of the Invention
The present invention relates to semiconductor voltage generator circuits, and particularly to capacitive voltage multiplier circuits.
2. Description of the Related Art
Many integrated circuits, particularly those using a single power supply voltage, incorporate on-chip circuitry to generate a “boosted” voltage having a magnitude greater than the power supply voltage. Frequently this boosted voltage is used as a veritable power supply voltage for portions of the circuitry contained on the integrated circuit. For example, certain types of semiconductor memories, such as “flash” EEPROM memories, write a memory cell by accelerating electrons across a tunneling dielectric and storing the charge on a floating gate above a field effect transistor. On contemporary devices, this acceleration of charge across the tunneling dielectric frequently requires a “write voltage” on the order of 8 volts, yet the remainder of the operations of the memory circuitry typically requires a voltage on the order of only 3 volts, including reading the memory cells. Unlike many older devices which require two different power supply voltages be supplied to operate the device (e.g., +5 and +12 volts), many contemporary devices require only a single power supply voltage (usually called VDD) equal to 2.5-3.3 volts (relative to “ground” or VSS). This VDD power supply voltage is typically utilized to power most of the device, including the normal read operation circuits. The write voltage (frequently, although not always, called VPP for legacy reasons) is generated by an on-chip voltage generator having a typical value of +8 volts (again relative to VSS) rather than requiring a separate power supply voltage be supplied by a user of the device.
In many integrated circuits, such on-chip voltage generators are implemented as capacitive voltage multiplier circuits, largely because of the historical ease of implementing suitably large capacitors on a monolithic integrated circuit, especially compared to implementing good quality inductors. These capacitive voltage multiplier circuits are usually called “charge pumps” by those in the art. Not to be confused with capacitive voltage multiplier circuits, there is another class of circuits also frequently called charge pumps. These are frequently used to integrate small current pulses generated each cycle by a phase detector circuit, and to consequently generate an analog voltage on a capacitor node which represents the phase error between two phase detector input signals. During each cycle, a typical phase detector “pumps” a first current pulse into the capacitor node and “pumps” a second current pulse from the capacitor node. If the phase error is zero, these two current pulses are equal, and the voltage on the capacitor node is unchanged. But if the phase of one input signal lags the other, one of the current pulses is greater in magnitude, or longer in duration, or both, so that the net charge into the capacitor node is non-zero, and a voltage change results. Such “phase detector integrator” charge pumps are quite different in both function and structure, and are consequently not considered to be related to capacitive voltage multiplier circuits. Consequently, as used herein, a “charge pump” refers to a capacitive voltage multiplier circuit and not to such phase detector integrator circuits, unless the context so requires.
In the nonvolatile memory example described above, the write voltage generated by the charge pump is typically higher than the VDD power supply voltage provided to the device. In other integrated circuits, a charge pump may be used to generate a voltage below the reference voltage VSS (i.e., “below ground”). For example, a negative bias voltage is generated in many memory devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and other circuits, to bias a substrate and/or a CMOS well within the substrate.
A traditional (and very well known) charge pump circuit for generating a boosted voltage above VDD is taught by John F. Dickson in “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976, pp. 374-378. Such a charge pump includes a plurality of serially-connected charge pump stages. Each charge pump stage includes a charge transfer device, such as a diode, and a pump capacitor, and has an input node and an output node. Complementary clock signals for use with such circuits are usually driven with fall VDD-level swings (i.e., transitioning between a low level of VSS and a high level of VDD).
Moreover, such voltage generator circuits also may consume a significant amount of power relative to the remainder of the circuit, and thus increase the current that must be supplied by the user (e.g., by the VDD power supply). In addition, such voltage generator circuits also may also require a significant amount of semiconductor real estate for their implementation, particularly if a high output current or large magnitude voltage is required.